Fábio Maia

Computer Engineer, Security Researcher, Indiehacker

Operating Systems: Linux Kernel, seL4, Android (Init, Zygote, SELinux), Debian (systemd, GNU, POSIX)
Reverse Engineering: Android (Java, JNI), Linux C/C++, ARM, ImHex, Ghidra, JADX, Frida
Firmware: bootloaders, device trees (DTB/DTS), TrustZone
Hardware Design: VHDL, RTL, Xilinx Vitis, USB C
Hardware Security: TrustZone, OP-TEE, Intel SGX, Secure Boot
Networking: TCP, TLS, HTTP, X.509, PKI (OpenSSL, Golang, Python)

Experience

Oct 2025 – present Freelancing

Reverse engineering consulting
BrainSpeed.ai, Explorar.dev, Reverser.dev

Jul 2022 – Jul 2025 Lead Reverse Engineer @ Bliq

AOSP build system, SELinux policy, Init, Bionic libc, C/C++
Reverse engineering TrustZone firmware, bootloaders, kernels, Android userspace
Linux kernel build, kernel modules, device tree (DTB/DTS), device drivers
Hardware reverse engineering, USB C protocols, flashing protocols
Lead team of embedded engineers and security researchers

Feb 2020 – Jul 2022 Reverse Engineer @ Bliq

Reverse engineering Android applications, Google Play Services, and private HTTP API.
Android ADB scripting, Linux server sysadmin (systemd, iptables, GNU coreutils), POSIX shell
TLS, PKI, X.509 (Python, OpenSSL, Golang)

2017-2018 Undergrad Research @ University of Aveiro

Published How to Choose the Best Tool for Each Task (Code Quality, Biomedical NLP).
Developed LEMA (Three.js, WebGL) for mathematics early childhood education.
Forked university LaTeX dissertation template into a new official location on GitHub

2007-2015 Early Career: Forum Software & Web Development

Built plugins and themes for MyBB forum software (PHP, MySQL, JavaScript)
Self-taught web development and Linux system administration
Community technical support, documentation, and tutorials

Education

2017-2019 MSc Computer Engineering @ University of Aveiro

CPU/GPU microarchitecture, CUDA programming, SoC Codesign (VHDL, C/C++)
Cybersecurity (X.509 PKI, TLS, AES, SHA, RSA)
Deep Learning (MATLAB, TensorFlow), Transfer Learning (VGG16, Inception, ResNet)

2014-2017 BSc Computer Engineering @ University of Aveiro

Digital hardware design in VHDL, FPGA, Altera, Xilinx
Embedded systems, PIC32 microcontroller programming, Cisco ISP networking
OS design, Linux userspace programming, Linux filesystems
MIPS CPU architecture, MIPS assembly, C/C++, Java